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summary
Annex A, R/C A, in 240-Pin, 72 bit-wide, PC3(L)-6400/PC3(L)-8500/PC3(L)-10600/PC3(L)-12800/PC3(L)-14900/PC3(L)-17000 DDR3 SDRAM Load Reduced DIMM Design Specification
Details
Publisher
JEDEC
File size
231.08 KB
Pages
18
Format
PDF
Publication date
2014-12-01
