JEDEC JEP122G provides reliability models and acceleration factors for common semiconductor device failure mechanisms.
Failure Mechanisms and Models for Semiconductor Devices is JEDEC Publication No. 122G, a technical reliability reference for semiconductor devices. It provides guidance on failure mechanisms, acceleration factors, apparent activation energies, and modeling parameters used to estimate system failure rates from accelerated stress test data.
The publication covers front-end, back-end, packaging, and interfacial mechanisms including time-dependent dielectric breakdown, hot carrier injection, negative bias temperature instability, electromigration, corrosion, stress migration, temperature cycling fatigue, interfacial failure, intermetallic and oxidation failures, tin whiskers, PCB ionic mobility, reliability data analysis, and design of experiments for model parameter determination.
Application Scope: Intended for semiconductor reliability engineering, device qualification, accelerated life testing, failure rate estimation, and reliability model selection for aluminum and copper metallization, low-k dielectrics, polysilicon or salicide gates, thin SiO2 gate dielectrics, silicon p-n junction isolation, tin whisker growth kinetics, and printed circuit board ionic mobility.
