BS EN 16603-20-40:2023 - Page 4

Space engineering. ASIC, FPGA and IP Core engineering. | Status: Current

1 Scope This standard specifies a comprehensive set of engineering requirements for the successful development of digital, analogue and mixed analogue-digital signal custom designed integrated circuits, such as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and Intellectual Property Cores (IP Cores), from now on referred to with the single and generic term DEVICEs. Microelectronics systems created by more than one DEVICE die but that are interconnected and packaged together as a single DEVICE are not considered single monolithic DEVICEs. However ECSS‑ST‑20‑40 is to be applied to (a) the development of each individual monolithic die, (b) also for their integration onto a multi-die single DEVICE considering those dice as IP Cores. This standard may be tailored for the specific characteristic and constraints of a space project in conformance with ECSS‑S‑ST‑00. A pre-tailoring based on the actual DEVICE type and criticality category of the DEVICE is addressed in clause 5.1.2. This standard does not cover requirements for the selection, control, procurement or usage of DEVICEs for space projects nor DEVICEESCC qualification requirements, as those requirements are covered by ECSS‑Q‑ST‑60C EEE components standard and the ESCC generic specification No. 9000 respectively. Nevertheless, this standard contemplates the possibility for the DEVICE to undergo ESCC qualification after the DEVICE customer acceptance as an ECSS qualified DEVICE, and thus a DEVICEESCC Detail Specification and DEVICE Radiation Test Plan and Report are optional expected outputs.