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ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
Details
Publisher
JEDEC
File size
1.21 MB
Pages
16
Format
PDF
Publication date
1996-12-01
